Tim2 And Tim3 Counter (Tim2_Cnt And Tim3_Cnt); Tim2 And Tim3 Prescaler (Tim2_Psc And Tim3_Psc); Tim2 And Tim3 Auto-Reload Register (Tim2_Arr And Tim3_Arr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
Note: The state of the external IO pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.
16.4.10

TIM2 and TIM3 counter (TIM2_CNT and TIM3_CNT)

Address offset: 0x24
Reset value: 0x00000000
31 30 29
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15 14 13
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Bits 31:16 CNT[31:16]: High counter value (on TIM2).
Bits 15:0 CNT[15:0]: Low counter value
16.4.11

TIM2 and TIM3 prescaler (TIM2_PSC and TIM3_PSC)

Address offset: 0x28
Reset value: 0x0000
15 14 13
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Bits 15:0 PSC[15:0]: Prescaler value
16.4.12

TIM2 and TIM3 auto-reload register (TIM2_ARR and TIM3_ARR)

Address offset: 0x2C
Reset value: 0x00000000
31 30 29
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15 14 13
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Bits 31:16 ARR[31:16]: High auto-reload value (on TIM2).
Bits 15:0
28 27 26 25
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12 11 10 9
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12 11 10 9
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The counter clock frequency CK_CNT is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event.
28 27 26 25
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12 11 10 9
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ARR[15:0]: Low Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to Section 16.3.1: Time-base unit on page 293
behavior.
The counter is blocked while the auto-reload value is null.
Doc ID 018940 Rev 1
General-purpose timers (TIM2 and TIM3)
24 23 22
CNT[31:16] (TIM2 only)
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8 7 6
CNT[15:0]
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8 7 6
PSC[15:0]
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24 23 22
ARR[31:16] (TIM2 only)
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8 7 6
ARR[15:0]
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21 20 19 18
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5 4 3 2
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5 4 3 2
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/ (PSC[15:0] + 1).
CK_PSC
21 20 19 18
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5 4 3 2
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for more details about ARR update and
17 16
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1 0
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1 0
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17 16
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1 0
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