Figure 52. Counter Timing Diagram, Internal Clock Divided By 1; Figure 53. Counter Timing Diagram, Internal Clock Divided By 2 - STMicroelectronics STM32F05 series Reference Manual

Advanced-control timers (TIM1)
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn't change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
●
The repetition counter is reloaded with the content of TIMx_RCR register
●
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
●
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

Figure 52. Counter timing diagram, internal clock divided by 1

Figure 53. Counter timing diagram, internal clock divided by 2

230/742
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow (cnt_udf)
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Doc ID 018940 Rev 1
05 04 03 02 01 00 36 35 34 33 32 31 30 2F
0002 0001 0000 0036 0035 0034 0033
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