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Inter-integrated circuit (I
23.7.9
PEC register (I2Cx_PECR)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PEC[7:0] Packet error checking register
Note:
If the SMBus feature is not supported, this register is reserved and forced by hardware to
"0x00000000". Please refer to
23.7.10
Receive data register (I2Cx_RXDR)
Address offset: 0x24
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 RXDATA[7:0] 8-bit receive data
532/742
2
C) interface
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This field contains the internal PEC when PECEN=1.
The PEC is cleared by hardware when PE=0 or when SWRST is set.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Data byte received from the I
Doc ID 018940 Rev 1
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Section 23.3: I2C
implementation.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
2
C bus.
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
PEC[7:0]
r
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
RXDATA[7:0]
r
RM0091
17
16
Res.
Res.
1
0
17
16
Res.
Res.
1
0
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