STMicroelectronics STM32F05 series Reference Manual page 521

RM0091
Bit 7 ERRIE: Error interrupts enable
Note: Any of these errors generate an interrupt:
Bit 6 TCIE: =Transfer Complete interrupt enable
0: Transfer Complete interrupt disabled
1: Transfer Complete interrupt enabled
Note: Any of these events will generate an interrupt:
Bit 5 STOPIE: STOP detection Interrupt enable
Bit 4 NACKIE: Not acknowledge received Interrupt enable
Bit 3 ADDRIE: Address match Interrupt enable (slave only)
Bit 2 RXIE: RX Interrupt enable
Bit 1 TXIE: TX Interrupt enable
Bit 0 PE: Peripheral enable
0: Error detection interrupts disabled
1: Error detection interrupts enabled
Arbitration Loss (ARLO)
Bus Error detection (BERR)
Overrun/Underrun (OVR)
Timeout detection (TIMEOUT)
PEC error detection (PECERR)
Alert pin event detection (ALERT)
Transfer Complete (TC)
Transfer Complete Reload (TCR)
0: Stop detection (STOPF) interrupt disabled
1: Stop detection (STOPF) interrupt enabled
0: Not acknowledge (NACKF) received interrupts disabled
1: Not acknowledge (NACKF) received interrupts enabled
0: Address match (ADDR) interrupts disabled
1: Address match (ADDR) interrupts enabled
0: Receive (RXNE) interrupt disabled
1: Receive (RXNE) interrupt enabled
0: Transmit (TXIS) interrupt disabled
1: Transmit (TXIS) interrupt enabled
0: Peripheral disable
1: Peripheral enable
Doc ID 018940 Rev 1
Inter-integrated circuit (I
2
C) interface
521/742