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RM0091
Table 46.
TIM1 register map and reset values (continued)
Offset
Register
TIM1_CCR1
0x34
Reset value
TIM1_CCR2
0x38
Reset value
TIM1_CCR3
0x3C
Reset value
TIM1_CCR4
0x40
Reset value
TIM1_BDTR
0x44
Reset value
TIM1_DCR
0x48
Reset value
TIM1_DMAR
0x4C
Reset value
Refer to
Section 2.2.2 on page 37
Doc ID 018940 Rev 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
for the register boundary addresses.
Advanced-control timers (TIM1)
CCR1[15:0]
0
0
0
0
0
0
0
0
0
CCR2[15:0]
0
0
0
0
0
0
0
0
0
CCR3[15:0]
0
0
0
0
0
0
0
0
0
CCR4[15:0]
0
0
0
0
0
0
0
0
0
LOCK
DT[7:0]
[1:0]
0
0
0
0
0
0
0
0
0
DBL[4:0]
0
0
0
0
0
0
DMAB[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DBA[4:0]
0
0
0
0
0
0
0
0
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