Tim1 Status Register (Tim1_Sr) - STMicroelectronics STM32F05 series Reference Manual

Advanced-control timers (TIM1)
15.4.5

TIM1 status register (TIM1_SR)

Address offset: 0x10
Reset value: 0x0000
15 14 13
Res. Res. Res. CC4OF CC3OF CC2OF CC1OF
rc_w0
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CC4OF: Capture/Compare 4 overcapture flag
Bit 11 CC3OF: Capture/Compare 3 overcapture flag
Bit 10 CC2OF: Capture/Compare 2 overcapture flag
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
Bit 8 Reserved, must be kept at reset value.
Bit 7 BIF: Break interrupt flag
Bit 6 TIF: Trigger interrupt flag
Bit 5 COMIF: COM interrupt flag
Bit 4 CC4IF: Capture/Compare 4 interrupt flag
Bit 3 CC3IF: Capture/Compare 3 interrupt flag
272/742
12 11 10 9
rc_w0 rc_w0 rc_w0
refer to CC1OF description
refer to CC1OF description
refer to CC1OF description
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to '0'.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
This flag is set by hardware as soon as the break input goes active. It can be cleared by
software if the break input is not active.
0: No break event occurred.
1: An active level has been detected on the break input.
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode.It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE,
CCxNE, OCxM - have been updated). It is cleared by software.
0: No COM event occurred.
1: COM interrupt pending.
refer to CC1IF description
refer to CC1IF description
Doc ID 018940 Rev 1
8 7 6 5
Res. BIF TIF COMIF
rc_w0 rc_w0 rc_w0
4 3 2
CC4IF CC3IF CC2IF CC1IF
rc_w0 rc_w0 rc_w0 rc_w0
RM0091
1 0
UIF
rc_w0