Receive Data Register (Usart_Rdr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
25.7.10

Receive data register (USART_RDR)

Address offset: 0x24
Reset value: Undefined
31 30 29
Res Res Res
15 14 13
Res Res Res
Bits 31:9 Reserved, must be kept at reset value.
Bits 8:0 RDR[8:0]: Receive data value
Universal synchronous asynchronous receiver transmitter (USART)
28 27 26 25
Res Res Res Res
12 11 10 9
Res Res Res Res
Contains the received data character.
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure
When receiving with the parity enabled, the value read in the MSB bit is the received parity
bit.
Doc ID 018940 Rev 1
24 23 22
Res Res Res
8 7 6
r r r
228).
21 20 19 18
Res Res Res Res
5 4 3 2
RDR[8:0]
r r r r
17 16
Res Res
1 0
r r
631/742