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Analog-to-digital converter (ADC)
Lower resolution reduces the conversion time needed for the successive approximation
steps as shown in
Table 34.
RES[1:0]
bits
12
10
8
6
12.5.3
End of conversion, end of sampling phase (EOC, EOSMP flags)
The ADC indicates each end of conversion (EOC) event.
The ADC sets the EOC flag in the ADC_ISR register as soon as a new conversion data
result is available in the ADC_DR register. An interrupt can be generated if the EOCIE bit is
set in the ADC_IER register. The EOC flag is cleared by software either by writing 1 to it, or
by reading the ADC_DR register.
The ADC also indicates the end of sampling phase by setting the EOSMP flag in the
ADC_ISR register. The EOSMP flag is cleared by software by writing1 to it. An interrupt can
be generated if the EOSMPIE bit is set in the ADC_IER register.
The aim of this interrupt is to allow the processing to be synchronized with the conversions.
Typically, an analog multiplexer can be accessed in hidden time during the conversion
phase, so that the multiplexer is positioned when the next sampling starts.
Note:
As there is only a very short time left between the end of the sampling and the end of the
conversion, it is recommenced to use polling or a WFE instruction rather than an interrupt
and a WFI instruction.
12.5.4
End of conversion sequence (EOSEQ flag)
The ADC notifies the application of each end of sequence (EOSEQ) event.
The ADC sets the EOSEQ flag in the ADC_ISR register as soon as the last data result of a
conversion sequence is available in the ADC_DR register. An interrupt can be generated if
the EOSEQIE bit is set in the ADC_IER register. The EOSEQ flag is cleared by software by
writing 1 to it.
180/742
Table
34.
t
timings depending on resolution
SAR
t
SAR
t
(ns) at
SAR
(ADC clock
f
= 14 MHz
ADC
cycles)
12.5
893 ns
11.5
821 ns
9.5
678 ns
7.5
535 ns
Doc ID 018940 Rev 1
t
t
SMPL (min)
(ADC clock cycles)
(ADC clock
cycles)
(with min. t
1.5
1.5
1.5
1.5
RM0091
ADC
t
(µs) at
ADC
f
= 14 MHz
ADC
SMPL)
14
1000 ns
13
928 ns
11
785 ns
9
643 ns
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