Figure 264. I 2 S Block Diagram - STMicroelectronics STM32F05 series Reference Manual

RM0091
Figure 264. I
MOSI/ SD
MISO
NSS/WS
CK
MCK
1. The MISO pin is not used in I
The SPI can function as an audio I
the I2SMOD bit in the SPIx_I2SCFGR register). This interface mainly uses the same pins,
flags and interrupts as the SPI.
2
The I S shares three common pins with the SPI:
●
SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time-
multiplexed data channels (in simplex mode only).
●
WS: Word Select (mapped on the NSS pin) is the data control signal output in master
mode and input in slave mode.
●
CK: Serial Clock (mapped on the SCK pin) is the serial clock output in master mode
and serial clock input in slave mode.
2
S block diagram
Master control logic
SPI
baud rate generator
I2S_CK
I2SMOD
2
S mode.
Doc ID 018940 Rev 1
Serial peripheral interface / inter-IC sound (SPI/I2S)
Address and data bus
Tx buffer
16-bit
Shift register
16-bit
Rx buffer
I2SCFG
[1:0]
Bidi
mode
LSB
First SPE BR2 BR1 BR0
2
I S clock generator
MCKOE ODD
2
S interface when the I
CH
BSY OVR MODF CRC
UDR
SIDE
ERR
LSB first Communication
control
CH
I2SSTD
CKPOL DATLEN
LEN
[1:0] [1:0]
I2S
I2SE
MOD
Bidi CRC CRC Rx
DFF SSM SSI
OE EN Next
only
MSTR CPOL CPHA
I2SDIV[7:0]
I2SxCLK
2
S capability is enabled (by setting
TxE RxNE
ai14748
653/742