Table 69. Examples Of Timings Settings For Fi2Cclk = 48 Mhz - STMicroelectronics STM32F05 series Reference Manual

Inter-integrated circuit (I
Table 69. Examples of timings settings for f
Parameter
10 kHz
PRESC
SCLL 0xC7
t 200 x 250 ns = 50 µs
SCLL
SCLH 0xC3
t 196 x 250 ns = 49 µs
SCLH
(1)
t ~100 µs
SCL
SDADEL
t 2 x 250 ns = 500 ns
SDADEL
SCLDEL
t 5 x 250 ns = 1250 ns
SCLDEL
t
1. The SCL period is greater than
SCL
examples.
2. t t minimum value is 4x t
SYNC1 + SYNC2
3. t t minimum value is 4x t
SYNC1 + SYNC2
4. t t minimum value is 4x t
SYNC1 + SYNC2
500/742
2
C) interface
Standard mode
100 kHz
0xB
20 x 250 ns = 5.0 µs
16 x 250 ns = 4.0 µs
(2)
~10 µs
0x2
2 x 250 ns = 500 ns
0x4
5 x 250 ns = 1250 ns
t + t
SCLL SCLH
= 83.3 ns. Example with t
I2CCLK
= 83.3 ns. Example with t
I2CCLK
= 83.3 ns. Example with t
I2CCLK
Doc ID 018940 Rev 1
= 48 MHz
I2CCLK
0xB
0x13
10 x 125 ns = 1250 ns
0xF
4 x 125 ns = 500 ns
(2)
~2500 ns
0x2
3 x 125 ns = 375 ns
0x4
4 x 125 ns = 500 ns
due to the SCL internal detection delay. Values provided for
SYNC1 +
SYNC1 +
SYNC1 +
Fast Mode Fast Mode Plus
400 kHz
5
0x9
4 x 125 ns = 500 ns
0x3
2 x 125 ns = 250 ns
(3)
0x3
0x3
2 x 125 ns = 250 ns
t = 1000 ns
SYNC2
t = 750 ns
SYNC2
t = 250 ns
SYNC2
RM0091
1000 kHz
5
0x3
0x1
(4)
~875 ns
0x0
0 ns
0x1
t
are only
SCL