Adc Sampling Time Register (Adc_Smpr); Adc Watchdog Threshold Register (Adc_Tr) - STMicroelectronics STM32F05 series Reference Manual

Analog-to-digital converter (ADC)
12.12.6

ADC sampling time register (ADC_SMPR)

Address offset: 0x14
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:3 Reserved, must be kept at reset value.
Bits 2:0 SMP[2:0]: Sampling time selection
These bits are written by software to select the sampling time that applies to all channels.
000: 1.5 ADC clock cycles
001: 7.5 ADC clock cycles
010: 13.5 ADC clock cycles
011: 28.5 ADC clock cycles
100: 41.5 ADC clock cycles
101: 55.5 ADC clock cycles
110: 71.5 ADC clock cycles
111: 239.5 ADC clock cycles
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
12.12.7

ADC watchdog threshold register (ADC_TR)

Address offset: 0x20
Reset value: 0x0000 0FFF
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:28 Reserved, must be kept at reset value.
Bit 27:16 HT[11:0]: Analog watchdog higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Refer to
AWD) on page 187
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bits 15:12 Reserved, must be kept at reset value.
200/742
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
28 27 26 25
12 11 10 9
rw rw rw
Section 12.8: Analog window watchdog (AWDEN, AWDSGL, AWDCH, AWD_HTR/LTR,
Doc ID 018940 Rev 1
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
Res. Res. Res. Res.
24 23 22 21
HT[11:0]
8 7 6 5
LT[11:0]
rw rw rw rw
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
Res. Res. SMP[2:0]
rw
20 19 18 17
4 3 2 1
rw rw rw rw
RM0091
16
Res.
0
16
0
rw