Tsc I/O Group X Counter Register (Tsc_Iogxcr) (X=1; Tsc Register Map; Table 101. Tsc Register Map And Reset Values - STMicroelectronics STM32F05 series Reference Manual

Advanced arm-based 32-bit mcus
Table of Contents

Advertisement

RM0091
Bits 5:0 GxE: Analog I/O group x enable
27.6.10

TSC I/O group x counter register (TSC_IOGxCR) (x=1..6)

Address offset: 0x30 + 0x04 x Analog I/O group number
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
r
Bits 31:14 Reserved, must be kept at reset value.
Bits 13:0 CNT[13:0]: Counter value
These bits represent the number of charge transfer cycles generated on the analog I/O
group x to complete its acquisition (voltage across C
27.6.11

TSC register map

Table 101. TSC register map and reset values

Offset
Register
TSC_CR
0x0000
Reset value
0
TSC_IER
0x0004
Reset value
TSC_ICR
0x0008
Reset value
TSC_ISR
0x000C
Reset value
TSC_IOHCR
0x0010
Reset value
0x0014
TSC_IOASCR
0x0018
Reset value
0x001C
These bits are set and cleared by software to enable/disable the acquisition (counter is
counting) on the corresponding analog I/O group x.
0: Acquisition on analog I/O group x disabled
1: Acquisition on analog I/O group x enabled
28
27
26
25
Res.
Res.
Res.
12
11
10
9
r
r
r
r
CTPH[3:0]
CTPL[3:0]
0
0
0
0
0
0
0
0
1
0
Doc ID 018940 Rev 1
24
23
22
Res.
Res.
Res.
8
7
6
CNT[13:0]
r
r
r
SSD[6:0]
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
Reserved
0
0
0
0
0
0
0
0
0
Reserved
Touch sensing controller (TSC)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
r
r
r
r
has reached the threshold).
S
MCV[2:0]
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
17
16
Res.
Res.
1
0
r
r
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
697/742

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the STM32F05 series and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Table of Contents