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Embedded Flash memory
3.5.3
Flash option key register (FLASH_OPTKEYR)
Address offset: 0x08
Reset value: xxxx xxxx
All the register bits are all write-only and will return a 0 when read.
31
30
29
w
w
w
15
14
13
w
w
w
Bits 31:0
OPTKEYR: Option byte key
3.5.4
Flash status register (FLASH_SR)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:6 Reserved, must be kept at reset value.
54/742
28
27
26
25
w
w
w
w
12
11
10
9
w
w
w
w
These bits represent the keys to unlock the OPTWRE.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Bit 5 EOP: End of operation
Set by hardware when a Flash operation (programming / erase) is completed.
Reset by writing a 1
Note: EOP is asserted at the end of each successful program or erase operation
Bit 4 WRPRTERR: Write protection error
Set by hardware when programming a write-protected address of the Flash
memory.
Reset by writing 1.
Bit 3 Reserved, must be kept at reset value.
Bit 2 PGERR: Programming error
Set by hardware when an address to be programmed contains a value different
from '0xFFFF' before programming.
Reset by writing 1.
Note: The STRT bit in the FLASH_CR register should be reset before starting a
programming operation.
Bit 1 Reserved, must be kept at reset value
Bit 0 BSY: Busy
This indicates that a Flash operation is in progress. This is set on the beginning
of a Flash operation and reset when the operation finishes or when an error
occurs.
Doc ID 018940 Rev 1
24
23
22
OPTKEYR[31:16]
w
w
w
8
7
6
OPTKEYR[15:0]
w
w
w
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
EOP
21
20
19
18
w
w
w
w
5
4
3
2
w
w
w
w
21
20
19
18
Res.
Res.
Res.
5
4
3
2
WRPRT
PG
Res.
ERR
ERR
rw
rw
rw
RM0091
17
16
w
w
1
0
w
w
17
16
Res.
Res.
1
0
Res.
BSY
r
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