Comp Registers; Comp Control And Status Register (Comp_Csr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
14.4

COMP registers

14.4.1

COMP control and status register (COMP_CSR)

Address offset : 0x1C
Reset value: 0x0000 0000
31 30 29 28
COMP COMP COMP2HYST
2LOCK 2OUT [1:0]
rwo r rw/r rw/r
15 14 13 12
COMP COMP COMP1HYST
1LOCK 1OUT [1:0]
rwo r rw/r rw/r
Bit 31 COMP2LOCK: Comparator 2 lock
Bit 30 COMP2OUT: Comparator 2 output
Bits 29:28 COMP2HYST[1:0] Comparator 2 hysteresis
Bit 27 COMP2POL: Comparator 2 output polarity
Bits 26:24 COMP2OUTSEL[2:0]: Comparator 2 output selection
27 26 25 24
COMP
COMP2OUTSEL[2:0]
2POL
rw/r rw/r rw/r rw/r
11 10 9
COMP
COMP1OUTSEL[2:0]
1POL
rw/r rw/r rw/r rw/r
This bit is write-once. It is set by software. It can only be cleared by a system reset.
It allows to have all control bits of comparator 2 as read-only.
0 : COMP_CSR[31:16] bits are read-write.
1 : COMP_CSR[31:16] bits are read-only.
This read-only bit is a copy of comparator 2 output state.
0 : Output is low (non-inverting input below inverting input).
1 : Output is high (non-inverting input above inverting input).
These bits control the hysteresis level.
00 : No hysteresis
01 : Low hysteresis
10 : Medium hysteresis
11 : High hysteresis
Please refer to the electrical characteristics for the hysteresis values.
This bit is used to invert the comparator 2 output.
0 : Output is not inverted
1 : Output is inverted
These bits select the destination of the comparator output.
000: No selection
001: Timer 1 break input
010: Timer 1 Input capture 1
011: Timer 1 OCrefclear input
100: Timer 2 input capture 4
101: Timer 2 OCrefclear input
110: Timer 3 input capture 1
111: Timer 3 OCrefclear input
Doc ID 018940 Rev 1
23 22 21
WNDW
COMP2INSEL[2:0]
EN
rw/r rw/r rw/r
8 7 6 5
Res. COMP1INSEL[2:0]
rw/r rw/r
Comparator (COMP)
20 19 18 17
COMP2MODE
Res.
[1:0]
rw/r rw/r rw/r
4 3 2 1
COMP1MODE COMP1
[1:0] SW1
rw/r rw/r rw/r rw/r
16
COMP2
EN
rw/r
0
COMP1
EN
rw/r
219/742