Figure 106. Counter Timing Diagram, Internal Clock Divided By 2; Figure 107. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36; Figure 108. Counter Timing Diagram, Internal Clock Divided By N - STMicroelectronics STM32F05 series Reference Manual

General-purpose timers (TIM2 and TIM3)

Figure 106. Counter timing diagram, internal clock divided by 2

Figure 107. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

1. Center-aligned mode 2 or 3 is used with an UIF on overflow.

Figure 108. Counter timing diagram, internal clock divided by N

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CK_INT
CNT_EN
TImer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow (cnt_ovf)
Update event (UEV)
Update interrupt flag (UIF)
CK_INT
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
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