Dma Request; Dac Registers; Dac Control Register (Dac_Cr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
Note: TSELx[2:0] bit cannot be changed when the ENx bit is set.
When software trigger is selected, the transfer from the DAC_DHRx register to the
DAC_DORx register takes only one APB1 clock cycle.
13.4

DMA request

Each DAC channel has a DMA capability. Two DMA channels are used to service DAC
channel DMA requests.
A DAC DMA request is generated when an external trigger (but not a software trigger)
occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred
to the DAC_DORx register.
DMA underrun
The DAC DMA request is not queued so that if a second external trigger arrives before the
acknowledgement for the first external trigger is received (first request), then no new request
is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set,
reporting the error condition. DMA data transfers are then disabled and no further DMA
request is treated. The DAC channelx continues to convert old data.
The software should clear the DMAUDRx flag by writing "1", clear the DMAEN bit of the
used DMA stream and re-initialize both DMA and DAC channelx to restart the transfer
correctly. The software should modify the DAC trigger conversion frequency or lighten the
DMA workload to avoid a new DMA. Finally, the DAC conversion can be resumed by
enabling both DMA data transfer and conversion trigger.
For each DAC channel, an interrupt is also generated if the corresponding DMAUDRIEx bit
in the DAC_CR register is enabled.
13.5

DAC registers

Refer to
The peripheral registers have to be accessed by words (32-bit).
13.5.1

DAC control register (DAC_CR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 13
DMAU DMA
Res. Res.
DRIE1 EN1
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Section 1.1 on page 34
28 27 26 25
Res
12 11 10 9
Res.
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Doc ID 018940 Rev 1
for a list of abbreviations used in register descriptions.
24 23 22
Res.
8 7 6
Res.
Digital-to-analog converter (DAC1)
21 20 19 18
Res. Res.
5 4 3 2
TSEL1[2:0] TEN1
rw rw rw rw
17 16
Res. Res.
1 0
BOFF1 EN1
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