Figure 198. Setup And Hold Timings - STMicroelectronics STM32F05 series Reference Manual

Inter-integrated circuit (I

Figure 198. Setup and hold timings

●
When the SCL falling edge is internally detected, a delay is inserted before sending
SDA output. This delay is
T
SDADEL
The total SDA output delay is:
duration depends on these parameters:
t
SYNC1
–
–
–
–
In order to bridge the undefined region of the SCL falling edge, you must program SDADEL
in such a way that:
{t
f (max)
474/742
2
C) interface
SCL falling edge internal detection
SCL
SDA
SCL
SDA
impacts the hold time
t
SYNC1
SCL falling slope
When enabled, input delay brought by the analog filter: t
When enabled, input delay brought by the digital filter: t
Delay due to SCL synchronization to I2CCLK clock (2 to 3 I2CCLK periods)
+t -50ns - [(DNF +2 ) x t
HD;DAT (min)
Doc ID 018940 Rev 1
DATA HOLD TIME
t
SDADEL
SYNC1
SDA output delay
t h(SDA)
Data hold time
DATA SETUP TIME
SCLDEL
SCL stretched low by the slave transmitter
tsu (SDA)
Data setup time
t = SDADEL x t
SDADEL PRESC
t
HD;DAT .
+ [ SDADEL x (PRESC+1) x t
]} / {(PRESC +1) x t
I2CCLK
where
t = (PRESC+1) x t
PRESC
]
I2CCLK
50ns < t
.
AF AF
= DNF t
x
DNF
} <= SDADEL
I2CCLK
RM0091
MS19846V1
I2CCLK.
< 260 ns.
I2CCLK