Adc Interrupts; Table 37. Adc Interrupts - STMicroelectronics STM32F05 series Reference Manual

RM0091
12.11

ADC interrupts

An interrupt can be generated by any of the following events:
●
ADC power-up, when the ADC is ready (ADRDY flag)
●
End of any conversion (EOC flag)
●
End of a sequence of conversions (EOSEQ flag)
●
When an analog watchdog detection occurs (AWD flag)
●
When the end of sampling phase occurs (EOSMP flag)
●
when a data overrun occurs (OVR flag)
Separate interrupt enable bits are available for flexibility.
Table 37.
ADC ready
End of conversion
End of sequence of conversions
Analog watchdog status bit is set
End of sampling phase
Overrun
ADC interrupts
Interrupt event
Doc ID 018940 Rev 1
Analog-to-digital converter (ADC)
Event flag Enable control bit
ADRDY ADRDYIE
EOC
EOSEQ EOSEQIE
AWD
EOSMP EOSMPIE
OVR
EOCIE
AWDIE
OVRIE
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