Clock Source; Capture/Compare Channels; Figure 146. Control Circuit In Normal Mode, Internal Clock Divided By 1; Figure 147. Capture/Compare Channel (Example: Channel 1 Input Stage) - STMicroelectronics STM32F05 series Reference Manual

RM0091
17.3.3

Clock source

The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 146
without prescaler.

Figure 146. Control circuit in normal mode, internal clock divided by 1

Counter clock = CK_CNT = CK_PSC
17.3.4

Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 147
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

Figure 147. Capture/compare channel (example: channel 1 input stage)

The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
shows the behavior of the control circuit and the upcounter in normal mode,
CK_INT
CEN=CNT_EN
UG
CNT_INIT
Counter register
to Figure 149 give an overview of one capture/compare channel.
TI1
TI1F
filter
f downcounter
DTS
ICF[3:0]
TIMx_CCMR1
Doc ID 018940 Rev 1
31 32 33 34 35 36
TI1F_Rising
0
TI1FP1
Edge
Detector
TI1F_Falling
1
CC1P/CC1NP
TIMx_CCER
TI2F_rising
0
(from channel 2)
TI2F_falling
1
(from channel 2)
General-purpose timer (TIM14)
00 01 02 03 04 05 06 07
TI1F_ED
to the slave mode controller
01
TI2FP1
IC1
divider
10
/1, /2, /4, /8
TRC
11
(from slave mode
controller)
CC1S[1:0] ICPS[1:0]
TIMx_CCMR1
IC1PS
CC1E
TIMx_CCER
359/742