Capture/Compare Channels; Figure 116. Capture/Compare Channel (Example: Channel 1 Input Stage); Figure 117. Capture/Compare Channel 1 Main Circuit - STMicroelectronics STM32F05 series Reference Manual

RM0091
16.3.4

Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
The following figure gives an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

Figure 116. Capture/compare channel (example: channel 1 input stage)

The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.

Figure 117. Capture/compare channel 1 main circuit

read CCR1H
read CCR1L
CC1S[1]
CC1S[0]
IC1PS
CC1E
CC1G
TIMx_EGR
TI1
TI1F
filter
f downcounter
DTS
ICF[3:0]
TIMx_CCMR1
S
read_in_progress
Capture/Compare Preload Register
R
capture_transfer
input
mode
Capture/Compare Shadow Register
Doc ID 018940 Rev 1
General-purpose timers (TIM2 and TIM3)
TI1F_Rising
TI1FP1
Edge
Detector
TI1F_Falling
CC1P/CC1NP
TIMx_CCER
TI2F_rising
(from channel 2)
TI2F_falling
(from channel 2)
APB Bus
MCU-peripheral interface
8
8
compare_transfer
capture
Counter
TI1F_ED
to the slave mode controller
01
TI2FP1
IC1
divider
10
/1, /2, /4, /8
TRC
11
(from slave mode
controller)
CC1S[1:0] ICPS[1:0]
TIMx_CCMR1
write CCR1H
S
write_in_progress
write CCR1L
R
output
mode
UEV
(from time
comparator
base unit)
CNT>CCR1
CNT=CCR1
IC1PS
CC1E
TIMx_CCER
CC1S[1]
CC1S[0]
OC1PE
OC1PE
TIMx_CCMR1
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