System configuration controller (SYSCFG)
Bit 12 TIM17_DMA_RMP: TIM17 DMA request remapping bit
Bit 11 TIM16_DMA_RMP: TIM16 DMA request remapping bit
Bit 10 USART1_RX_DMA_RMP: USART1_RX DMA request remapping bit
Bit 9 USART1_TX_DMA_RMP: USART1_TX DMA remapping bit
Bit 8 ADC_DMA_RMP: ADC DMA remapping bit
Bits 7:2 Reserved, must be kept at reset value.
Bits 1:0 MEM_MODE[1:0]: Memory mapping selection bits
9.1.2
SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1)
Address offset: 0x08
Reset value: 0x0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
EXTI3[3:0]
rw
rw
rw
136/742
This bit is set and cleared by software. It controls the remapping of TIM17 DMA request.
0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1)
1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2)
This bit is set and cleared by software. It controls the remapping of TIM16 DMA request.
0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4)
This bit is set and cleared by software. It controls the remapping of USART1_RX DMA
request.
0: No remap (USART1_RX DMA request mapped on DMA channel 3)
1: Remap (USART1_RX DMA request mapped on DMA channel 5)
This bit is set and cleared by software. It bit controls the remapping of USART1_TX DMA
request.
0: No remap (USART1_TX DMA request mapped on DMA channel 2)
1: Remap (USART1_TX DMA request mapped on DMA channel 4)
This bit is set and cleared by software. It controls the remapping of ADC DMA request.
0: No remap (ADC DMA request mapped on DMA channel 1)
1: Remap (ADC DMA request mapped on DMA channel 2)
These bits are set and cleared by software. They control the memory internal mapping at
address 0x0000 0000. After reset these bits take on the memory mapping selected by
BOOT0 pin and nBOOT1 option bit.
x0: Main Flash memory mapped at 0x0000 0000
01: System Flash memory mapped at 0x0000 0000
11: Embedded SRAM mapped at 0x0000 0000
28
27
26
25
Res.
Res.
Res.
12
11
10
9
EXTI2[3:0]
rw
rw
rw
rw
Doc ID 018940 Rev 1
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
EXTI1[3:0]
rw
rw
rw
rw
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
EXTI0[3:0]
rw
rw
rw
rw
RM0091
16
Res.
0
rw
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