Figure 54. Counter Timing Diagram, Internal Clock Divided By 4; Figure 55. Counter Timing Diagram, Internal Clock Divided By N; Figure 56. Counter Timing Diagram, Update Event When Repetition Counter - STMicroelectronics STM32F05 series Reference Manual

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Figure 54. Counter timing diagram, internal clock divided by 4

Figure 55. Counter timing diagram, internal clock divided by N

Figure 56. Counter timing diagram, update event when repetition counter

CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
is not used
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
Write a new value in TIMx_ARR
Doc ID 018940 Rev 1
Advanced-control timers (TIM1)
0001
0000
20 1F 00
05 04 03 02 01 00 36 35 34 33 32 31 30 2F
FF
0036 0035
36
36
231/742