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Real-time clock (RTC)
Table 82.
RTC register map and reset values (continued)
Offset
Register
RTC_SHIFTR
0x2C
Reset value
0
RTC_TSTR
0x30
Reset value
RTC_TSDR
0x34
Reset value
RTC_TSSSR
0x38
Reset value
RTC_ CALR
0x3C
Reset value
RTC_TAFCR
0x40
Reset value
RTC_
ALRMASSR
0x44
Reset value
RTC_BKP0R
0x50
Reset value
0
to 0x60
to RTC_BKP4R
Reset value
0
Refer to
570/742
0
MASKSS[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Section 2.2.2 on page 37
Doc ID 018940 Rev 1
0
HU[3:0]
0
0
0
0
0
0
0
0
WDU[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BKP[31:0]
0
0
0
0
0
0
0
0
0
BKP[31:0]
0
0
0
0
0
0
0
0
0
for the register boundary addresses.
SUBFS[14:0]
0
0
0
0
0
0
0
0
0
MNU[3:0]
ST[2:0]
0
0
0
0
0
0
0
0
MU[3:0]
[1:0]
0
0
0
0
0
0
0
SS[15:0]
0
0
0
0
0
0
0
0
0
CALM[8:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SS[14:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0091
0
0
0
0
0
SU[3:0]
0
0
0
0
0
DT
DU[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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