Tim2 And Tim3 Capture/Compare Enable Register; Tim3_Ccer) - STMicroelectronics STM32F05 series Reference Manual

Advanced arm-based 32-bit mcus
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RM0091
Input capture mode
Bits 15:12 IC4F: Input capture 4 filter
Bits 11:10 IC4PSC: Input capture 4 prescaler
Bits 9:8 CC4S: Capture/Compare 4 selection
Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
Bits 7:4 IC3F: Input capture 3 filter
Bits 3:2 IC3PSC: Input capture 3 prescaler
Bits 1:0 CC3S: Capture/Compare 3 selection
Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
16.4.9
TIM2 and TIM3 capture/compare enable register (TIM2_CCER and

TIM3_CCER)

Address offset: 0x20
Reset value: 0x0000
15
14
13
CC4NP
Res.
CC4P
CC4E
rw
rw
Bit 15 CC4NP: Capture/Compare 4 output Polarity.
Bit 14
Bit 13 CC4P: Capture/Compare 4 output Polarity.
Bit 12 CC4E: Capture/Compare 4 output enable.
Bit 13 CC3NP: Capture/Compare 3 output Polarity.
Bit 12
Bits 11:10
Bit 9 CC3P: Capture/Compare 3 output Polarity.
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
12
11
10
9
CC3NP
Res.
CC3P
rw
rw
rw
Refer to CC1NP description
Reserved, always read as 0.
Refer to CC1P description
Refer to CC1E description
Refer to CC1NP description
Reserved, always read as 0.
Reserved, always read as 0.
Refer to CC1P description
Doc ID 018940 Rev 1
General-purpose timers (TIM2 and TIM3)
8
7
6
5
CC3E
CC2NP
Res.
CC2P
rw
rw
rw
4
3
2
1
CC2E
CC1NP
Res.
CC1P
rw
rw
rw
0
CC1E
rw
343/742

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