STMicroelectronics STM32F05 series Reference Manual page 619

RM0091
Bit 15 DEP: Driver enable polarity selection
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept
This bit can only be written when the USART is disabled (UE=0).
Bit 14 DEM: Driver enable mode
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept
This bit can only be written when the USART is disabled (UE=0).
Bit 13 DDRE: DMA Disable on Reception Error
Note: The reception errors are: parity error, framing error or noise error.
Bit 12 OVRDIS: Overrun Disable
Note: This control bit allows checking the communication flow w/o reading the data.
Bit 11 ONEBIT: One sample bit method enable
This bit can only be written when the USART is disabled (UE=0).
Bit 10 CTSIE: CTS interrupt enable
Note: If the hardware flow control feature is not supported, this bit is reserved and forced by
Universal synchronous asynchronous receiver transmitter (USART)
0: DE signal is active high.
1: DE signal is active low.
cleared. Please refer to
This bit allows the user to activate the external transceiver control, through the DE signal.
0: DE function is disabled.
1: DE function is enabled. The DE signal is output on the RTS pin.
cleared. Section 25.4: USART implementation on page
0: DMA is not disabled in case of reception error. The corresponding error flag is set but
RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not
asserted, so the erroneous data is not transferred (no DMA request), but next correct
received data will be transferred. (used for Smartcard mode)
1: DMA is disabled following a reception error. The corresponding error flag is set, as well as
RXNE. The DMA request is masked until the error flag is cleared. This means that the
software must first disable the DMA request (DMAR = 0) or clear RXNE before clearing the
error flag.
This bit can only be written when the USART is disabled (UE=0).
This bit is used to disable the receive overrun detection.
0: Overrun Error Flag, ORE, is set when received data is not read before receiving new
data.
1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set
the ORE flag is not set and the new received data overwrites the previous content of the
USART_RDR register.
This bit can only be written when the USART is disabled (UE=0).
This bit allows the user to select the sample method. When the one sample bit method is
selected the noise detection flag (NF) is disabled.
0: Three sample bit method
1: One sample bit method
0: Interrupt is inhibited
1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register
hardware to '0'. Please refer to
Doc ID 018940 Rev 1
Section 25.4: USART implementation on page
Section 25.4: USART implementation on page
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