Rtc Smooth Digital Calibration - STMicroelectronics STM32F05 series Reference Manual

Real-time clock (RTC)
When the RTC_REFIN detection is enabled, PREDIV_A and PREDIV_S must be set to their
default values:
●
PREDIV_A = 0x007F
●
PREVID_S = 0x00FF
Note: RTC_REFIN clock detection is not available in Standby mode.
24.3.11

RTC smooth digital calibration

The RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a
range from -487.1 ppm to +488.5 ppm. The correction of the frequency is performed using
series of small adjustments (adding and/or subtracting individual RTCCLK pulses). These
adjustments are fairly well distributed so that the RTC is well calibrated even when observed
over short durations of time.
The smooth digital calibration is performed during a cycle of about 2
32 seconds when the input frequency is 32768 Hz.
The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles
to be masked during the 32-second cycle:
●
Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32-
second cycle.
●
Setting CALM[1] to 1 causes two additional cycles to be masked
●
Setting SMC[2] to 1 causes four additional cycles to be masked
●
and so on up to SMC[8] set to 1 which causes 256 clocks to be masked.
While CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine
resolution, the bit CALP can be used to increase the frequency by 488.5 ppm. Setting CALP
to '1' effectively inserts an extra RTCCLK pulse every 2
that 512 clocks are added during every 32-second cycle.
Using CALM together with CALP, an offset ranging from -511 to +512 RTCCLK cycles can
be added during the 32-second cycle, which translates to a calibration range of -487.1 ppm
to +488.5 ppm with a resolution of about 0.954 ppm.
The formula to calculate the effective calibrated frequency (F
(F
RTCCLK
F
CAL
Calibration when PREDIV_A<3
The CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in
RTC_PRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are
set to a value less than 3, CALP is ignored and the calibration operates as if CALP was
equal to 0.
To perform a calibration with PREDIV_A less than 3, the synchronous prescaler value
(PREDIV_S) should be reduced so that each second is accelerated by 8 RTCCLK clock
cycles, which is equivalent to adding 256 clock cycles every 32 seconds. As a result,
between?255 and 256 clock pulses (corresponding to a calibration range from ?243.3 to
244.1 ppm) can effectively be added during each 32-second cycle using only the CALM bits.
With a nominal RTCCLK frequency of 32768 Hz, when PREDIV_A equals 1 (division factor
of 2), PREDIV_S should be set to 16379 rather than 16383 (4 less). The only other
544/742
) is as follows:
= F x [ 1 + (CALP x 512 - CALM) / (2
RTCCLK
Doc ID 018940 Rev 1
20
RTCCLK pulses, or
11
RTCCLK cycles, which means
) given the input frequency
CAL
20
+ CALM - CALP x 512) ]
RM0091