Hardware Flow Control And Rs485 Driver Enable; Figure 248. Reception Using Dma; Figure 249. Hardware Flow Control Between 2 Usarts - STMicroelectronics STM32F05 series Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)

Figure 248. Reception using DMA

TX line
RXNE flag
DMA request
USART_DR
DMA reads USART_DR
DMA TCIF flag
(Transfer complete)
software configures the
DMA to receive 3 data
blocks and enables
the USART
Error flagging and interrupt generation in multibuffer communication
In multibuffer communication if any error occurs during the transaction the error flag is
asserted after the current byte. An interrupt is generated if the interrupt enable flag is set.
For framing error, overrun error and noise flag which are asserted with RXNE in single byte
reception, there is a separate error flag interrupt enable bit (EIE bit in the USART_CR3
register), which, if set, enables an interrupt after the current byte if any of these errors occur.
25.5.16

Hardware flow control and RS485 Driver Enable

It is possible to control the serial data flow between 2 devices by using the nCTS input and
the nRTS output. The

Figure 249. Hardware flow control between 2 USARTs

RTS and CTS flow control can be enabled independently by writing the RTSE and CTSE
bits respectively to 1 (in the USART_CR3 register).
606/742
Frame 1
DMA reads F1
from
USART_DR
Figure 249
USART 1
TX
TX circuit
nCTS
RX
RX circuit
nRTS
Doc ID 018940 Rev 1
Frame 2
set by hardware
cleared by DMA read
F1
DMA reads F2
from
USART_DR
shows how to connect 2 devices in this mode:
RX
nRTS
TX
nCTS
Frame 3
F2
set by hardware
DMA reads F3 The DMA transfer
from
USART_DR
USART 2
RX circuit
TX circuit
RM0091
F3
cleared
by software
is complete
(TCIF=1 in
DMA_ISR)
ai17193b