Tim16 And Tim17 Dma Control Register (Tim16_Dcr And Tim17_Dcr); Tim16 And Tim17 Dma Address For Full Transfer; Tim17_Dmar) - STMicroelectronics STM32F05 series Reference Manual

General-purpose timers (TIM15/16/17)
18.6.14

TIM16 and TIM17 DMA control register (TIM16_DCR and TIM17_DCR)

Address offset: 0x48
Reset value: 0x0000
15 14 13
Res. Res. Res.
Bits 15:13 Reserved, always read as 0.
Bits 12:8 DBL[4:0]: DMA burst length
This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address), i.e. the number of
transfers. Transfers can be in half-words or in bytes (see example below).
00000: 1 transfer,
00001: 2 transfers,
00010: 3 transfers,
...
10001: 18 transfers.
Bits 7:5 Reserved, always read as 0.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bits vector defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In
this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..
18.6.15 TIM16 and TIM17 DMA address for full transfer (TIM16_DMAR and

TIM17_DMAR)

Address offset: 0x4C
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 DMAB[15:0]: DMA register for burst accesses
A read or write access to the DMAR register accesses the register located at the address:
"(TIMx_CR1 address) + DBA + (DMA index)" in which:
TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address
configured in TIMx_DCR register, DMA index is the offset automatically controlled by the
DMA transfer, depending on the length of the transfer DBL in the TIMx_DCR register.
436/742
12 11 10 9
DBL[4:0]
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12 11 10 9
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Doc ID 018940 Rev 1
8 7 6 5
Res. Res. Res.
rw
8 7 6 5
DMAB[15:0]
rw rw rw rw
4 3 2 1
DBA[4:0]
rw rw rw rw
4 3 2 1
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RM0091
0
rw
0
rw