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Digital-to-analog converter (DAC1)
Bits 31:16 Reserved, must be kept at reset value.
Bit 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software which specifies 12-bit data for DAC channel1.
Bits 3:0 Reserved, must be kept at reset value.
13.5.5
DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel1.
13.5.6
DAC channel1 data output register (DAC_DOR1)
Address offset: 0x2C
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:12 Reserved, must be kept at reset value.
Bit 11:0 DACC1DOR[11:0]: DAC channel1 data output
These bits are read-only, they contain data output for DAC channel1.
212/742
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
r
r
r
r
Doc ID 018940 Rev 1
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
DACC1DHR[7:0]
rw
rw
rw
rw
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
DACC1DOR[11:0]
r
r
r
r
RM0091
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
rw
rw
rw
rw
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
r
r
r
r
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