Interrupt & Status Register (Usart_Isr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
25.7.8 Interrupt & status register (USART_ISR)
Address offset: 0x1C
Reset value: 0x00C0
31 30 29
Res Res Res
15 14 13
ABRF ABRE Res EOBF
r r
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 REACK: Receive enable acknowledge flag
This bit is set/reset by hardware, when the Receive Enable value is taken into account by the
USART.
It can be used to verify that the USART is ready for reception before entering Stop mode.
Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and
Bit 21 TEACK: Transmit enable acknowledge flag
This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the
USART.
It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in
the USART_CR1 register, in order to respect the TE=0 minimum period.
Bit 20 WUF: Wakeup from Stop mode flag
This bit is set by hardware, when a wakeup event is detected. The event is defined by the
WUS bit field. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register.
An interrupt is generated if WUFIE=1 in the USART_CR3 register.
Note: 1. When UESM is cleared, WUF flag is also cleared.
Bit 19 RWU: Receiver wakeup from Mute mode
Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and
Universal synchronous asynchronous receiver transmitter (USART)
28 27 26 25
Res Res Res Res
12 11 10 9
RTOF CTS CTSIF
r r r r
forced by hardware to '0'.
2. The WUF interrupt is active only in Stop mode.
3. If the USART does not support the wakeup from Stop feature, this bit is reserved and
forced by hardware to '0'.
This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a
wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE)
is selected by the WAKE bit in the USART_CR1 register.
When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the
MMRQ bit in the USART_RQR register.
0: Receiver in active mode
1: Receiver in mute mode
forced by hardware to '0'.
Doc ID 018940 Rev 1
24 23 22 21
RE TE
Res Res
ACK ACK
r r
8 7 6 5
LBDF TXE TC RXNE
r r r r
20 19 18 17
WUF RWU SBKF CMF
r r r r
4 3 2 1
IDLE ORE NF FE
r r r r
16
BUSY
r
0
PE
r
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