Figure 19. Dma Request Mapping - STMicroelectronics STM32F05 series Reference Manual

Direct memory access controller (DMA)

Figure 19. DMA request mapping

Peripheral request signals
I2C1_TX, TIM1_CH1,
TIM2_UP, TIM3_CH3,
I2C1_RX, TIM1_CH2,
TIM3_CH4, TIM3_UP,
I 2C2_TX, USART2_TX,
TIM1_CH4,TIM1_TRIG,
TIM1_COM, TIM2_CH4,
TIM3_CH1,TIM3_TRIG,
I2C2_RX, USART2_RX,
TIM1_CH3, TIM1_UP,
TIM2_CH1, TIM15_CH1,
TIM15_UP,TIM15_TRIG,
1. DMA request mapped on this DMA channel only if the corresponding remapping bit is cleared in the
SYSCFG_CFGR1 register. For more details, please refer to
1 (SYSCFG_CFGR1) on page
2. DMA request mapped on this DMA channel only if the corresponding remapping bit is set in the
SYSCFG_CFGR1 register. For more details, please refer to
1 (SYSCFG_CFGR1) on page
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(1)
ADC , TIM2_CH3,
TIM17_CH1,
(1)
TIM17_UP
(2)
ADC
, SPI1_RX,
(1)
USART1_TX ,
(2)
TIM17_CH1 ,
(2)
TIM17_UP
SPI1_TX,
( ) 1
USART1_RX
,
TIM2_CH2,
TIM6_UP, DAC,
1 ( )
TIM16_CH1 ,
1 ( )
TIM16_UP
SPI2_RX,
(2)
USART1_TX ,
(2)
TIM16_CH1 ,
(2)
TIM16_UP
SPI2_TX,
(2)
USART1_RX ,
TIM15_COM
135.
135.
Doc ID 018940 Rev 1
DMA
HW request 1
SW trigger 1
(MEM2MEM bit)
HW request 2
SW trigger 2
MEM2MEM bit)
HW request 3
SW trigger 3
MEM2MEM bit)
HW request 4
SW trigger 4
MEM2MEM bit)
HW request 5
SW trigger 5
MEM2MEM bit)
Section 9.1.1: SYSCFG configuration register
Section 9.1.1: SYSCFG configuration register
Fixed hardware priority
High priority
Channel 1
Channel 2
Internal
Channel 3
request
Channel 4
Channel 5
Low priority
MS19219V2
RM0091
DMA