Clock Configuration Register 2 (Rcc_Cfgr2) - STMicroelectronics STM32F05 series Reference Manual

RM0091
7.4.12

Clock configuration register 2 (RCC_CFGR2)

Address: 0x2C
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access
31 30 29
Res Res Res
15 14 13
Res Res Res
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 PREDIV[3:0] PREDIV division factor
These bits are set and cleared by software to select PREDIV1 division factor. They can be
written only when the PLL is disabled.
Note: Bit 0 is the same bit as bit17 in
0000: HSE input to PLL not divided
0001: HSE input to PLL divided by 2
0010: HSE input to PLL divided by 3
0011: HSE input to PLL divided by 4
0100: HSE input to PLL divided by 5
0101: HSE input to PLL divided by 6
0110: HSE input to PLL divided by 7
0111: HSE input to PLL divided by 8
1000: HSE input to PLL divided by 9
1001: HSE input to PLL divided by 10
1010: HSE input to PLL divided by 11
1011: HSE input to PLL divided by 12
1100: HSE input to PLL divided by 13
1101: HSE input to PLL divided by 14
1110: HSE input to PLL divided by 15
1111: HSE input to PLL divided by 16
28 27 26 25
Res Res Res Res
12 11 10 9
Res Res Res Res
bit17 Clock configuration register (RCC_CFGR)
configuration register 2 (RCC_CFGR2)
Doc ID 018940 Rev 1
24 23 22 21
Res Res Res Res
8 7 6 5
Res Res Res Res
Clock configuration register
aslo modifies bit 0 in
( for compatibility with other STM32 products)
Reset and clock control (RCC)
20 19 18
Res Res Res
4 3 2
Res PREDIV[3:0]
rw rw
(RCC_CFGR), so modifying
Clock
17 16
Res Res
1 0
rw rw
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