Smbus Initialization - STMicroelectronics STM32F05 series Reference Manual

Inter-integrated circuit (I
SMBus
23.4.12
This section is relevant only when SMBus feature is supported. Please refer to
I2C implementation.
In addition to I2C initialization, some other specific initialization must be done in order to
perform SMBus communication:
Received Command and Data Acknowledge control (Slave mode)
A SMBus receiver must be able to NACK each received command or data. In order to allow
ACK control in slave mode, the Slave Byte Control mode must be enabled by setting the
SBC bit in the I2Cx_CR1 register. Refer to
details.
Specific address (Slave mode)
The specific SMBus addresses should be enabled if needed. Refer to
page 503
●
The SMBus Device Default address (0b1100 001) is enabled by setting the SMBDEN
bit in the I2Cx_CR1 register.
● The SMBus Host address (0b0001 000) is enabled by setting the SMBHEN bit in the
I2Cx_CR1 register.
●
The Alert Response Address (0b0001100) is enabled by setting the ALERTEN bit in
the I2Cx_CR1 register.
Packet error checking
PEC calculation is enabled by setting the PECEN bit in the I2Cx_CR1 register. Then the
PEC transfer is managed with the help of a hardware byte counter: NBYTES[7:0] in the
I2Cx_CR2 register. The PECEN bit must be configured before enabling the I2C.
The PEC transfer is managed with the hardware byte counter, so the SBC bit must be set
when interfacing the SMBus in slave mode. The PEC is transferred after NBYTES-1 data
have been transferred when the PECBYTE bit is set and the RELOAD bit is cleared. If
RELOAD is set, PECBYTE has no effect.
Caution: Changing the PECEN configuration is not allowed when the I2C is enabled.
Table 71.
Master Tx/Rx NBYTES + PEC+ STOP
Master Tx/Rx NBYTES + PEC + ReSTART
504/742
2
C) interface
initialization
for more details.
SMBUS with PEC configuration table
Mode
Slave Tx/Rx with PEC
Doc ID 018940 Rev 1
Slave Byte Control Mode on page 480
SBC RELOAD
bit bit
x 0
x 0
1 0
RM0091
Section 23.3:
for more
Bus idle detection on
AUTOEND PECBYTE
bit bit
1 1
0 1
x 1