Reset and clock control (RCC)
7.4.11
AHB peripheral reset register (RCC_AHBRSTR)
Address: 0x28
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access
31
30
29
Res
Res
Res
15
14
13
Res
Res
Res
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 TSCRST: Touch sensing controller reset
Set and cleared by software.
0: No effect
1: Reset TSC
Bit 23 Reserved, must be kept at reset value.
Bit 22 IOPFRST: I/O port F reset
Set and cleared by software.
0: No effect
1: Reset I/O port F
Bit 21 Reserved, must be kept at reset value.
Bit 20 IOPDRST: I/O port D reset
Set and cleared by software.
0: No effect
1: Reset I/O port D
Bit 19 IOPCRST: I/O port C reset
Set and cleared by software.
0: No effect
1: Reset I/O port C
Bit 18 IOPBRST: I/O port B reset
Set and cleared by software.
0: No effect
1: Reset I/O port B
Bit 17 IOPARST: I/O port A reset
Set and cleared by software.
0: No effect
1: Reset I/O port A
Bits 16:0 Reserved, must be kept at reset value.
112/742
28
27
26
25
Res
Res
Res
Res
12
11
10
9
Res
Res
Res
Res
Doc ID 018940 Rev 1
24
23
22
21
TSC
IOPF
Res
Res
RST
RST
rw
rw
8
7
6
5
Res
Res
Res
Res
20
19
18
17
IOPD
IOPC
IOPB
IOPA
RST
RST
RST
RST
rw
rw
rw
rw
4
3
2
1
Res
Res
Res
Res
RM0091
16
Res
0
Res
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