Spi Extended Features; I²S Features; Spi/I2S Implementation; Spi Functional Description - STMicroelectronics STM32F05 series Reference Manual

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26.1.2

SPI extended features

●
SPI TI mode support
26.1.3 I²S features
●
Simplex communication (only transmitter or receiver)
●
Master or slave operations
●
8-bit programmable linear prescaler to reach accurate audio sample frequencies (from
8 kHz to 192 kHz)
●
Data format may be 16-bit, 24-bit or 32-bit
● Packet frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, 32-bit data
frame) by audio channel
●
Programmable clock polarity (steady state)
●
Underrun flag in slave transmission mode, overrun flag in reception mode (master and
slave) and Frame Error Flag in reception and transmitter mode (slave only)
●
16-bit register for transmission and reception with one data register for both channel
sides
●
Supported I
–
–
–
–
●
Data direction is always MSB first
●
DMA capability for transmission and reception (16-bit wide)
●
Master clock can be output to drive an external audio component. Ratio is fixed at
256 × F
26.2

SPI/I2S implementation

This manual describes the full set of features implemented in SPI1. SPI2 supports all the
features except I²S mode.
26.3

SPI functional description

26.3.1

General description

The SPI allows synchronous, serial communication between the MCU and external devices.
Application software can manage the communication by polling the status flag or using
dedicated SPI interrupt. The main elements of SPI and their interactions are shown in the
following block diagram
2
S protocols:
2
I S Philips standard
MSB-Justified standard (Left-Justified)
LSB-Justified standard (Right-Justified)
PCM standard (with short and long frame synchronization on 16-bit channel frame
or 16-bit data frame extended to 32-bit channel frame)
(where F is the audio sampling frequency)
S S
Figure 253.
Doc ID 018940 Rev 1
Serial peripheral interface / inter-IC sound (SPI/I2S)
635/742