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Direct memory access controller (DMA)
Table 26.
DMA register map and reset values (continued)
Offset
Register
DMA_CPAR4
0x04C
Reset value
0
DMA_CMAR4
0x050
Reset value
0
0x054
DMA_CCR5
0x058
Reset value
0
DMA_CNDTR5
0x05C
Reset value
0
DMA_CPAR5
0x060
Reset value
0
DMA_CMAR5
0x064
Reset value
0
Refer to
156/742
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Section 2.2.2 on page 37
Doc ID 018940 Rev 1
PA[31:0]
0
0
0
0
0
0
0
0
0
MA[31:0]
0
0
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PA[31:0]
0
0
0
0
0
0
0
0
0
MA[31:0]
0
0
0
0
0
0
0
0
0
for the register boundary addresses.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PL
[1:0]
0
0
0
0
0
0
0
0
0
NDT[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0091
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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