Timeout Register (I2Cx_Timeoutr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
23.7.6

Timeout register (I2Cx_TIMEOUTR)

Address offset: 0x14
Reset value: 0x0000 0000
31 30 29
TEXTEN Res. Res.
rw
15 14 13
TIMOUTEN Res. Res.
rw
Bits 31 TEXTEN: Extended clock timeout enable
0: Extended clock timeout detection is disabled
1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more
than t
Bits 30:29 Reserved, must be kept at reset value.
Bits 27:16 TIMEOUTB[11:0]: Bus timeout B
This field is used to configure the cumulative clock extension timeout:
In master mode, the master cumulative clock low extend time (t
In slave mode, the slave cumulative clock low extend time (t
t
Note: These bits can be written only when TEXTEN=0.
Bit 15 TIMOUTEN: Clock timeout enable
0: SCL timeout detection is disabled
1: SCL timeout detection is enabled: when SCL is low for more than t
high for more than t
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 TIDLE: Idle clock timeout detection
0: TIMEOUTA is used to detect SCL low timeout
1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
Note: This bit can be written only when TIMOUTEN=0.
Bits 11:0 TIMEOUTA[11:0]: Bus Timeout A
This field is used to configure:
– The SCL low timeout condition t
t
– The bus idle condition (both SCL and SDA high) when TIDLE=1
t
Note: These bits can be written only when TIMOUTEN=0.
Note:
If the SMBus feature is not supported,
"0x00000000".
28 27 26
Res.
12 11 10
TIDLE
rw
is done by the I2C interface, a timeout error is detected (TIMEOUT=1).
TLOW:EXT
= (TIMEOUTB+1) x 2048 x t
TLOW:EXT
(TIDLE=1), a timeout error is detected (TIMEOUT=1).
IDLE
= (TIMEOUTA+1) x 2048 x t
TIMEOUT
= (TIMEOUTA+1) x 4 x t
IDLE
Please refer to Section 23.3: I2C
Doc ID 018940 Rev 1
Inter-integrated circuit (I
25 24 23 22
TIMEOUTB
rw
9 8 7 6
TIMEOUTA
rw
I2CCLK
when TIDLE=0
TIMEOUT
I2CCLK
I2CCLK
this register is reserved and forced by hardware to
implementation.
2
C) interface
21 20 19 18
5 4 3 2
) is detected
LOW:MEXT
) is detected
LOW:SEXT
(TIDLE=0) or
TIMEOUT
17 16
1 0
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