Sw-Dp State Machine (Reset, Idle States, Id Code); Dp And Ap Read/Write Accesses; Sw-Dp Registers; Table 111. Sw-Dp Registers - STMicroelectronics STM32F05 series Reference Manual

RM0091
29.5.3

SW-DP state machine (reset, idle states, ID code)

The State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It
follows the JEP-106 standard. This ID code is the default ARM one and is set to
0x1BA01477 (corresponding to Cortex-M0).
Note: Note that the SW-DP state machine is inactive until the target reads this ID code.
●
The SW-DP state machine is in RESET STATE either after power-on reset, or after the
line is high for more than 50 cycles
●
The SW-DP state machine is in IDLE STATE if the line is low for at least two cycles after
RESET state.
●
After RESET state, it is mandatory to first enter into an IDLE state AND to perform a
READ access of the DP-SW ID CODE register. Otherwise, the target will issue a
FAULT acknowledge response on another transactions.
Further details of the SW-DP state machine can be found in the Cortex-M0 TRM and the
CoreSight Design Kit r1p0 TRM.
29.5.4

DP and AP read/write accesses

●
Read accesses to the DP are not posted: the target response can be immediate (if
ACK=OK) or can be delayed (if ACK=WAIT).
● Read accesses to the AP are posted. This means that the result of the access is
returned on the next transfer. If the next access to be done is NOT an AP access, then
the DP-RDBUFF register must be read to obtain the result.
The READOK flag of the DP-CTRL/STAT register is updated on every AP read access
or RDBUFF read request to know if the AP read access was successful.
●
The SW-DP implements a write buffer (for both DP or AP writes), that enables it to
accept a write operation even when other transactions are still outstanding. If the write
buffer is full, the target acknowledge response is "WAIT". With the exception of
IDCODE read or CTRL/STAT read or ABORT write which are accepted even if the write
buffer is full.
●
Because of the asynchronous clock domains SWCLK and HCLK, two extra SWCLK
cycles are needed after a write transaction (after the parity bit) to make the write
effective internally. These cycles should be applied while driving the line low (IDLE
state)
This is particularly important when writing the CTRL/STAT for a power-up request. If the
next transaction (requiring a power-up) occurs immediately, it will fail.
29.5.5

SW-DP registers

Access to these registers are initiated when APnDP=0

Table 111. SW-DP registers

A(3:2)
00 Read
00 Write
CTRLSEL bit
R/W of SELECT
register
Doc ID 018940 Rev 1
Register
The manufacturer code is not set to ST code
IDCODE
0x2BA01477 (identifies the SW-DP)
ABORT
Debug support (DBG)
Notes
723/742