Control/Status Register (Rcc_Csr) - STMicroelectronics STM32F05 series Reference Manual

Reset and clock control (RCC)
7.4.10

Control/status register (RCC_CSR)

Address: 0x24
Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
31 30 29
IW
LPWR WWDG
WDG
RSTF RSTF RSTF
RSTF
rw rw rw
15 14 13
Res Res Res
Bit 31 LPWRRSTF: Low-power reset flag
Set by hardware when a Low-power management reset occurs.
Cleared by writing to the RMVF bit.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to
reset.
Bit 30 WWDGRSTF: Window watchdog reset flag
Set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWWDGRSTF: Independent window watchdog reset flag
Set by hardware when an independent watchdog reset from V
Cleared by writing to the RMVF bit.
0: No watchdog reset occurred
1: Watchdog reset occurred
Bit 28 SFTRSTF: Software reset flag
Set by hardware when a software reset occurs.
Cleared by writing to the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Bit 27 PORRSTF: POR/PDR reset flag
Set by hardware when a POR/PDR reset occurs.
Cleared by writing to the RMVF bit.
0: No POR/PDR reset occurred
1: POR/PDR reset occurred
110/742
28 27 26 25
SFT POR PIN
OB
LRSTF
RSTF RSTF
rw rw rw rw
12 11 10 9
Res Res Res Res
Doc ID 018940 Rev 1
24 23 22 21
RMVF Res Res Res
rw
8 7 6 5
Res Res Res Res
20 19 18 17
Res Res Res Res
4 3 2 1
LSI
Res Res Res
RDY
r
Low-power management
domain occurs.
DD
RM0091
16
Res
0
LSION
rw