Dma Registers; Dma Interrupt Status Register (Dma_Isr) - STMicroelectronics STM32F05 series Reference Manual

Direct memory access controller (DMA)
10.4

DMA registers

Refer to
The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32-
bit).
10.4.1

DMA interrupt status register (DMA_ISR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
TEIF4 HTIF4 TCIF4 GIF4
r r r
Bits 31:28 Reserved, must be kept at reset value.
Bits 19, 15, 11, 7, 3 TEIFx: Channel x transfer error flag (x = 1 ..5)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer error (TE) on channel x
1: A transfer error (TE) occurred on channel x
Bits 18, 14, 10, 6, 2 HTIFx: Channel x half transfer flag (x = 1 ..5)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No half transfer (HT) event on channel x
1: A half transfer (HT) event occurred on channel x
Bits 17, 13, 9, 5, 1 TCIFx: Channel x transfer complete flag (x = 1 ..5)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer complete (TC) event on channel x
1: A transfer complete (TC) event occurred on channel x
Bits 16, 12, 8, 4, 0 GIFx: Channel x global interrupt flag (x = 1 ..5)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No TE, HT or TC event on channel x
1: A TE, HT or TC event occurred on channel x
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Section 1.1 on page 34
27 26 25
Res. Res. Res.
11 10 9
TEIF3 HTIF3 TCIF3
r r r r
Doc ID 018940 Rev 1
for a list of abbreviations used in register descriptions.
24 23 22
Res. Res. Res. Res.
8 7 6
GIF3 TEIF2 HTIF2 TCIF2
r r r
21 20 19 18
Res. TEIF5 HTIF5
r r
5 4 3 2
GIF2 TEIF1 HTIF1
r r r r
RM0091
17 16
TCIF5 GIF5
r r
1 0
TCIF1 GIF1
r r