Rtc Clock; Watchdog Clock; Clock-Out Capability; Low Power Modes - STMicroelectronics STM32F05 series Reference Manual

Reset and clock control (RCC)
7.2.9

RTC clock

The RTCCLK clock source can be either the HSE/32, LSE or LSI clocks. This is selected by
programming the RTCSEL[1:0] bits in the
This selection cannot be modified without resetting the Backup domain. The system must be
always configured in a way that the PCLK frequency is greater then or equal to the RTCCLK
frequency for proper operation of the RTC.
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.
Consequently:
●
If LSE is selected as RTC clock:
–
●
If LSI is selected as the RTC clock:
–
●
If the HSE clock divided by 32 is used as the RTC clock:
–
7.2.10

Watchdog clock

If the Independent watchdog (IWWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWWDG.
7.2.11

Clock-out capability

The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. The configuration registers of the corresponding GPIO port must be
programmed in alternate function mode. One of 5 clock signals can be selected as the MCO
clock.
● HSI14
●
SYSCLK
● HSI
●
HSE
● PLL clock divided by 2
The selection is controlled by the MCO[2:0] bits of the
(RCC_CFGR).
7.3

Low power modes

APB peripheral clocks and DMA clock can be disabled by software.
Sleep mode stops the CPU clock. The memory interface clocks (Flash and RAM interfaces)
can be stopped by software during sleep mode. The AHB to APB bridge clocks are disabled
by hardware during Sleep mode when all the clocks of the peripherals connected to them
are disabled.
Stop mode stops all the clocks in the core supply domain and disables the PLL and the HSI,
HSI14 and HSE oscillators.
90/742
The RTC continues to work even if the V
V supply is maintained.
BAT
The RTC state is not guaranteed if the V
The RTC state is not guaranteed if the V
voltage regulator is powered off (removing power from the 1.8 V domain).
Doc ID 018940 Rev 1
Backup domain control register
supply is switched off, provided the
DD
supply is powered off.
DD
supply is powered off or if the internal
DD
Clock configuration register
RM0091
(RCC_BDCR).