Repetition Counter; Figure 62. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow) - STMicroelectronics STM32F05 series Reference Manual

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Figure 62. Counter timing diagram, Update event with ARPE=1 (counter overflow)

15.3.3

Repetition counter

Section 15.3.1: Time-base unit
respect to the counter overflows/underflows. It is actually generated only when the repetition
counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx
capture/compare registers in compare mode) every N counter overflows or underflows,
where N is the value in the TIMx_RCR repetition counter register.
The repetition counter is decremented:
●
At each counter overflow in upcounting mode,
●
At each counter underflow in downcounting mode,
●
At each counter overflow and at each counter underflow in center-aligned mode.
Although this limits the maximum number of repetition to 128 PWM cycles, it makes it
possible to update the duty cycle twice per PWM period. When refreshing compare
registers only once per PWM period in center-aligned mode, maximum resolution is
2xT
The repetition counter is an auto-reload type; the repetition rate is maintained as defined by
the TIMx_RCR register value (refer to
software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave
mode controller, it occurs immediately whatever the value of the repetition counter is and the
repetition counter is reloaded with the content of the TIMx_RCR register.
In center-aligned mode, for odd values of RCR, the update event occurs either on the
overflow or on the underflow depending on when the RCR register was written and when the
counter was started. If the RCR was written before starting the counter, the UEV occurs on
the overflow. If the RCR was written after starting the counter, the UEV occurs on the
underflow. For example for RCR = 3, the UEV is generated on each 4th overflow or
underflow event depending on when RCR was written.
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload active register
, due to the symmetry of the pattern.
ck
Doc ID 018940 Rev 1
CK_PSC
CEN
F7 F8 F9 FA FB FC
FD
FD
describes how the update event (UEV) is generated with
Figure 63). When the update event is generated by
Advanced-control timers (TIM1)
36 35 34 33 32 31 30 2F
36
36
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