STMicroelectronics STM32F05 series Reference Manual page 626

Universal synchronous asynchronous receiver transmitter (USART)
Bit 18 SBKF: Send break flag
Bit 17 CMF: Character match flag
Bit 16 BUSY: Busy flag
Bit 15 ABRF: Auto baud rate flag
Note: If the USART does not support the auto baud rate feature, this bit is reserved and
Bit 14 ABRE: Auto baud rate error
This bit is set by hardware if the baud rate measurement failed (baud rate out of range or
character comparison failed)
It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and
Bit 13 Reserved, must be kept at reset value.
Bit 12 EOBF: End of block flag
Note: If Smartcard mode is not supported, this bit is reserved and forced by hardware to '0'.
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This bit indicates that a send break character was requested. It is set by software, by writing
1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during
the stop bit of break transmission.
0: No break character is transmitted
1: Break character will be transmitted
This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is
cleared by software, writing 1 to the CMCF in the USART_ICR register.
An interrupt is generated if CMIE=1in the USART_CR1 register.
0: No Character match detected
1: Character Match detected
This bit is set and reset by hardware. It is active when a communication is ongoing on the
RX line (successful start bit detected). It is reset at the end of the reception (successful or
not).
0: USART is idle (no reception)
1: Reception on going
This bit is set by hardware when the automatic baud rate has been set (RXNE will also be
set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was
completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case)
It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to
the ABRRQ in the USART_RQR register.
forced by hardware to '0'.
forced by hardware to '0'.
This bit is set by hardware when a complete block has been received (for example T=1
Smartcard mode). The detection is done when the number of received bytes (from the start
of the block, including the prologue) is equal or greater than BLEN + 4.
An interrupt is generated if the EOBIE=1 in the USART_CR2 register.
It is cleared by software, writing 1 to the EOBCF in the USART_ICR register.
0: End of Block not reached
1: End of Block (number of characters) reached
Please refer to Section 25.4: USART implementation on page
Doc ID 018940 Rev 1
RM0091
573.