Power Control/Status Register (Pwr_Csr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
6.4.2

Power control/status register (PWR_CSR)

Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.
31 30 29
Res Res Res
15 14 13
Res Res Res
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 EWUP2: Enable WKUP2 pin
This bit is set and cleared by software.
0: WKUP2 pin is used for general purpose I/O. An event on the WKUP2 pin does not wakeup
the device from Standby mode.
1: WKUP2 pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP1 pin wakes-up the system from Standby mode).
Note: This bit is reset by a system Reset.
Bit 8 EWUP1: Enable WKUP1 pin
This bit is set and cleared by software.
0: WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does not wakeup
the device from Standby mode.
1: WKUP1 pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP1 pin wakes-up the system from Standby mode).
Note: This bit is reset by a system Reset.
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 PVDO: PVD output
This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.
0: V
1: V
Notes:
1.
2.
Bit 1 SBF: Standby flag
This bit is set by hardware when the device enters Standby mode and it is cleared only by a
POR/PDR (power on reset/power down reset) or by setting the CSBF bit in the
register (PWR_CR)
0: Device has not been in Standby mode
1: Device has been in Standby mode
28 27 26 25
Res Res Res Res
12 11 10 9
EWUP
Res Res Res
2
rw
is lower than the PVD threshold selected with the PLS[2:0] bits.
DD
is higher than the PVD threshold selected with the PLS[2:0] bits.
DD
The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after Standby
or reset until the PVDE bit is set.
Once the PVD is enabled and configured in the PWR_CR register, PVDO can be used to
generate an interrupt through the External Interrupt controller.
Doc ID 018940 Rev 1
24 23 22 21
Res Res Res Res
8 7 6
EWUP
Res Res Res
1
rw
Power control (PWR)
20 19 18
Res Res Res
5 4 3 2
Res Res PVDO
r
17 16
Res Res
1 0
SBF WUF
r r
Power control
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