Tolerance Of The Usart Receiver To Clock Deviation; Table 86. Tolerance Of The Usart Receiver When Brr[3:0] = 0000 - STMicroelectronics STM32F05 series Reference Manual

RM0091
25.5.5

Tolerance of the USART receiver to clock deviation

The asynchronous receiver of the USART works correctly only if the total clock system
deviation is less than the tolerance of the USART receiver. The causes which contribute to
the total deviation are:
● DTRA: Deviation due to the transmitter error (which also includes the deviation of the
transmitter's local oscillator)
●
DQUANT: Error due to the baud rate quantization of the receiver
●
DREC: Deviation of the receiver's local oscillator
●
DTCL: Deviation due to the transmission line (generally due to the transceivers which
can introduce an asymmetry between the low-to-high transition timing and the high-to-
low transition timing)
Where
when M = 1:
when M=0:
t
WUSTOP
datasheet.
The USART receiver can receive data correctly at up to the maximum tolerated deviation
specified in
● 10- or 11-bit character length defined by the M bit in the USART_CR1 register
●
Oversampling by 8 or 16 defined by the OVER8 bit in the USART_CR1 register
● Bits BRR[3:0] of USART_BRR register are equal to or different from 0000.
●
Use of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in
the USART_CR3 register
●
Table 86.
M bit
Universal synchronous asynchronous receiver transmitter (USART)
DTRA DQUANT DREC
+ +
DWU is the error due to sampling point deviation when the wakeup from Stop
mode is used.
is the wakeup time from Stop mode, which is specified in the product
Table 86 and Table
Tolerance of the USART receiver when BRR[3:0] = 0000
ONEBIT=0
0 3.75%
1 3.41%
Doc ID 018940 Rev 1
<
DTCL DWU Tolerance of the USART receiver
+ +
t
WUSTOP
DWU
= ----------------------------
( ×
11 Tbit
t
WUSTOP
DWU = ----------------------------
( ×
10 Tbit
87, depending on the following choices:
OVER8 bit = 0
ONEBIT=1
4.375%
3.97%
)
)
OVER8 bit = 1
ONEBIT=0
2.50%
2.27%
ONEBIT=1
3.75%
3.41%
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