Adc Clock; Figure 24. Enabling/Disabling The Adc - STMicroelectronics STM32F05 series Reference Manual

RM0091
Follow this procedure to disable the ADC:
●
Check that ADSTART=0 in the ADC_CR register to ensure that no conversion is
ongoing. If required, stop any ongoing conversion by writing 1 to the ADSTP bit in the
the ADC_CR register and waiting until this bit is read at 0.
●
Set ADDIS=1 in the ADC_CR register.
● If required by the application, wait until ADEN=0 in the ADC_CR register, indicating that
the ADC is fully disabled (ADDIS is automatically reset once ADEN=0).

Figure 24. Enabling/disabling the ADC

ADEN
ADRDY
ADDIS
ADC
stat
by S/W
Note: In auto-off mode (AUTOFF=1) the power-on/off phases are not performed by software
writing the ADEN/ADDIS control bits. However, ADRDY interrupts are still generated.
12.4.3

ADC clock

The ADC has a dual clock-domain architecture, so that the ADC clock (ADC_CLK) is
independent from the APB clock (PCLK).
The ADC_CLK can be generated from one of two possible clock source options which are
selected in the RCC registers (refer to
page 82):
●
Option 1: dedicated 14 MHz internal oscillator
●
Option 2: PCLK clock divided by 2 or divided by 4 (limited to a maximum ADC_CLK
frequency of 14 MHz)
Option 1 has the advantage of always having the optimum ADC clock frequency (14 MHz)
whatever the HCLK/PCLK clock scheme selected. It also provides the capability of using the
low power auto-off mode (to save power, the ADC interface can automatically switch the
14 MHz internal oscillator ON/OFF).
Option 2 has the advantage of avoiding any clock domain resynchronization. This can be
useful when the ADC is triggered by a timer and if the application requires that there is no
uncertainty (no jitter) in the duration between the trigger event and the start of the ADC. In
option 1, jitter is induced by the resynchronization of the trigger signal. To ensure there is no
jitter, the JITOFF_D2 or JITOFF_D4 bits must be properly configured in the ADC_CFGR2
register. These bits activate the appropriate jitter removal mechanism depending on the
PLCLK divider ratio.
t
STAB
OFF Startup RDY
by H/W
Doc ID 018940 Rev 1
Analog-to-digital converter (ADC)
CONVERTING CH
Section 7: Reset and clock control (RCC) on
REQ
RDY OFF
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