Communication Formats; Figure 258. Hardware/Software Slave Select Management - STMicroelectronics STM32F05 series Reference Manual

Serial peripheral interface / inter-IC sound (SPI/I2S)
Hardware or software slave select management can be set using the SSM bit in the
SPIx_CR1 register:
●
Software NSS management (SSM = 1): in this configuration, slave select information
is driven internally by the SSI bit value in register SPIx_CR1. The external NSS pin is
free for other application uses.
●
Hardware NSS management (SSM = 0): in this case, there are two possible
configurations. The configuration used depends on the NSS output configuration
(SSOE bit in register SPIx_CR1).
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Figure 258. Hardware/software slave select management

26.3.5

Communication formats

During SPI communication, receive and transmit operations are performed simultaneously.
The serial clock (SCK) synchronizes the shifting and sampling of the information on the data
lines. The communication format depends on the clock phase, the clock polarity and the
data frame format. To be able to communicate together, the master and slaves devices must
follow the same communication format.
Clock phase and polarity controls
Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits in the SPIx_CR1 register. The CPOL (clock polarity) bit controls the idle state value of
the clock when no data is being transferred. This bit affects both master and slave modes. If
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NSS output enable (SSM=0,SSOE = 1): this configuration is only used when the
MCU is set as master. The NSS pin is managed by the hardware. The NSS signal
is driven low as soon as the SPI is enabled in master mode (SPE=1), and is kept
low until the SPI is disabled (SPE =0). A pulse can be generated between
continuous communications if NSS pulse mode is activated (NSSP=1). The SPI
cannot work in multimaster configuration with this NSS setting.
NSS output disable (SSM=0, SSOE = 0): if the microcontroller is acting as the
master on the bus, this configuration allows multimaster capability. If the NSS pin
is pulled low in this mode, the SPI enters master mode fault state and the device is
automatically reconfigured in slave mode. In slave mode, the NSS pin works as a
standard "chip select" input and the slave is selected while NSS line is at low level.
NSS
NSS external
Doc ID 018940 Rev 1
SSM bit
SSI bit
1
0
Output
SSOE bit
control
(Master mode and hardware management only)
NSS Master Slave
Vdd OK Non active
Vss Conflict Active
NSS input
NSS output
ai14746b
RM0091