Figure 94. Counter Timing Diagram, Internal Clock Divided By 1; Figure 95. Counter Timing Diagram, Internal Clock Divided By 2; Figure 96. Counter Timing Diagram, Internal Clock Divided By 4 - STMicroelectronics STM32F05 series Reference Manual

Advanced arm-based 32-bit mcus
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General-purpose timers (TIM2 and TIM3)

Figure 94. Counter timing diagram, internal clock divided by 1

Figure 95. Counter timing diagram, internal clock divided by 2

Figure 96. Counter timing diagram, internal clock divided by 4

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CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
CK_INT
CNT_EN
TImer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
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0036
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0036
RM0091
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