STMicroelectronics STM32F05 series Reference Manual page 502

Inter-integrated circuit (I
Received Command and Data acknowledge control
A SMBus receiver must be able to NACK each received command or data. In order to allow
the ACK control in slave mode, the Slave Byte Control mode must be enabled by setting
SBC bit in I2Cx_CR1 register. Refer to
more details.
Host Notify protocol
This peripheral supports the Host Notify protocol by setting the SMBHEN bit in the
I2Cx_CR1 register. In this case the host will acknowledge the SMBus Host address (0b0001
000).
When this protocol is used, the device acts as a master and the host as a slave.
SMBus alert
The SMBus ALERT optional signal is supported. A slave-only device can signal the host
through the SMBALERT# pin that it wants to talk. The host processes the interrupt and
simultaneously accesses all SMBALERT# devices through the Alert Response Address
(0b0001 100). Only the device(s) which pulled SMBALERT# low will acknowledge the Alert
Response Address.
When configured as a slave device(SMBHEN=0), the SMBA pin is pulled low by setting the
ALERTEN bit in the I2Cx_CR1 register. The Alert Response Address is enabled at the same
time.
When configured as a host (SMBHEN=1), the ALERT flag is set in the I2Cx_ISR register
when a falling edge is detected on the SMBA pin and ALERTEN=1. An interrupt is
generated if the ERRIE bit is set in the I2Cx_CR1 register. When ALERTEN=0, the ALERT
line is considered high even if the external SMBA pin is low.
If the SMBus ALERT pin is not needed, the SMBA pin can be used as a standard GPIO if
ALERTEN=0.
Packet error checking
A packet error checking mechanism has been introduced in the SMBus specification to
improve reliability and communication robustness. Packet Error Checking is implemented by
appending a Packet Error Code (PEC) at the end of each message transfer. The PEC is
calculated by using the C(x) = x
(including addresses and read/write bits).
The peripheral embeds a hardware PEC calculator and allows to send a Not Acknowledge
automatically when the received byte does not match with the hardware calculated PEC.
Timeouts
This peripheral embeds hardware timers in order to be compliant with the 3 timeouts defined
in SMBus specification ver. 2.0.
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C) interface
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Doc ID 018940 Rev 1
Slave Byte Control Mode on page 480
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+ x + 1 CRC-8 polynomial on all the message bytes
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