RM0091
Figure 265. I
Data are latched on the falling edge of CK (for the transmitter) and are read on the rising
edge (for the receiver). The WS signal is also latched on the falling edge of CK.
Figure 266. I
This mode needs two write or read operations to/from the SPIx_DR register.
●
In transmission mode:
If 0x8EAA33 has to be sent (24-bit):
Figure 267. Transmitting 0x8EAA33
●
In reception mode:
If data 0x8EAA33 is received:
2
S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0)
CK
WS
SD
MSB
2
S Philips standard waveforms (24-bit frame with CPOL = 0)
CK
WS
Transmission
24-bit data
SD
MSB
Channel left 32-bit
First write to Data register
0x8EAA
Doc ID 018940 Rev 1
Serial peripheral interface / inter-IC sound (SPI/I2S)
Transmission
Reception
May be 16-bit or 32-bit
Channel left
Reception
8-bit remaining 0 forced
LSB
Second write to Data register
Only the 8 MSB are sent
to compare the 24 bits
8 LSBs have no meaning
and can be anything
LSB
MSB
Channel right
MS19591V1
Channel right
MS19592V1
0x33XX
MS19593V1
655/742
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